The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. Such IC devices are fabricated by patterning a sequence of patterned and un-patterned layers, and the features on successive patterned layers are spatially related to each other. During fabrication, each patterned layer must be aligned with the previous patterned layers with a degree of precision. Pattern alignment techniques typically provide an overlay mark to achieve alignment of successive layers. An exemplary overlay mark is a pattern forming a box (typically an open-centered box) used in a box-in-box (BIB) alignment technique. As device scaling continues, and multiple lithography processes are implemented for patterning a layer, overlay mark signals are becoming weaker, preventing precise alignment of the successive patterned layers. Accordingly, although existing alignment structures and methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.